ASIVA14 - Analog SImulation and Variability Analysis for 14nm designs
Marie Curie International Training Network (ITN, 09/2013 - 08/2017)
This ITN Research Project ASIVA14 is supported by the European Union in the FP7-PEOPLE-2013-ITN Program under Grant Agreement Number 608243 (FP7 Marie Curie Action, Project ASIVA14 - Analog SImulation and Variability Analysis for 14nm designs)
Why ASIVA14 ?
On April 17th, 2014, Samsung Electronics Co., Ltd. and GlobalFoundries Inc. announced a new strategic collaboration to deliver global capacity for 14 nanometer (nm) FinFET process technology (Samsung and GLOBALFOUNDRIES Forge Strategic Collaboration to Deliver Multi-Sourced Offering of 14nm FinFET Semiconductor Technology), and its mass production is scheduled for the end of 2014. The 14nm FinFET process is based on a technology platform that has already gained traction as the leading choice for high-volume, power-efficient System-on-Chip (SoC) designs, all while increasing performance (it's worth mentioning that the 14nm FinFET is not the technology all the industries are adopting. Instead, STMicroelectronics N.V., together with its parteners, develops Fully Depleted Silicon-On-Insulator (FD-SOI) transistor technology to further decrease power consumptions and to maintain low costs for the manifacturing process).
These three factors are awfully and equally important in the design and manifacture of today's complex electronic devices, whose application range from mobile and wireless, to computers, networks and storage, to the health-care, etc.. In fact, miniaturization of the electronic components (Moore's law) allows, e.g., to extend battery life of portable devices, potentially faster computations, patient monitoring through wearable medical devices.
However, miniaturization implies also an increased complexity in circuit design in the Electronic Design Automation (EDA) industry through diversification (More than Moore). Nowadays, many people still associate electronics primarily with digital technology, but the Analog and Mixed-Signal (AMS) content has grown in these products with every new node. In fact, nearly 70% of today’s designs can be considered mixed signal (think about complex Integrated Circuits (ICs) and Printed Circuit Boards (PCBs)). Modern SoCs integrate a very large number of cores and Intellectual Properties (IPs), digital, analog and Radio-Frequency (RF) circuit elements, manufactured using the most advanced technology nodes (28nm, 20nm and soon 10nm; 14nm of our proposal in between the last two).
The 28nm process node has once more raised the design bar in terms of the design-for-manufacturing checks needed to realize a design. This is particularly true for AMS engineering, where rules now need to be addressed in a more integrated, automated, and timely way.In order to meet the design and verification challenges faced by the semiconductor industry, hundreds of Computer Aided Design (CAD) tools developed by the EDA industry are used from early stage concept to manufacturing. EDA industry enables trillions of $ of goods and services to be sold each year. Although tremendous enhancements in speed, capacity and functionalities have been made by commercial and industry Spice simulators over the past years, there are still technical gaps that will be detailed below.
In recent years the demand of the electronics industry on mathematical methods used in EDA software has witnessed a tremendous growth. "The real world is analog and computers are digital."
Most current EDA methods and the tools that support them are inadequate to the task of designing for the “real world”, for to do so they must account for an enormous number of design considerations. The list is long and daunting for every application and includes Process, Voltage and Temperature (PVT) variation, power consumption, process constraints and yield requirements. Advanced numerical techniques are imperative to address present-day challenges (going to 14 nm!) in the electronics industry.
The motivation for this training network is the need for a network of highly educated European scientists in the field of mathematics for the EDA industry and computational science, so as to exchange and discuss current insights and ideas, and to lay groundwork for future collaborations. The challenge lies in the necessity of combining transferable techniques and skills such as mathematical analysis, sophisticated numerical methods and stochastic simulation methods, with deep qualitative and quantitative understanding of mathematical models arising from problems in the electronics and EDA industry. The main training objective is to prepare, at the highest possible level, young researchers with a broad scope of scientific knowledge and to teach transferable skills. The two partners in the project combine decades of knowledge on EDA problems, and as such are an ideal basis for the hosting of the young ESRs to be trained.
Scientific & Technical Objectives
Design and Verification (D&V) of mixed-signal SoCs can’t be handled using Spice or even FastSpice products. It is indeed impracticable to handle a large SoC at transistor level (billions of transistors), and therefore the industry has come up with various means to raise the abstraction level above transistor in order to simulate a true mixed-signal SoC with a digital engine and some abstraction of the analog IPs. It should be noticed that the speed limiting factor of a mixed-signal simulation is the analog engine, since digital simulators are orders of magnitude faster. Designers desperately need a comprehensive transistor-level design and verification framework comprised of methods, tools and underlying algorithms up to the task of analyzing, optimizing and verifying mixed-signal circuits within the given statistical manufacturing variations, and well before tape-out. This is not a small task. Today’s nanometer designs consist of literally thousands of variables that do not lend themselves well to simplifying assumptions.
Therefore, the objective of the ASIVA14 project is to develop advanced numerical methods and algorithms for the design, verification and variability analysis of Custom ICs at nanometer technology nodes (targeting 14 nm) to be integrated within leading edge transistor-level simulators.
Work Packages - Project Structure
WP 1: Innovative numerical methods for Nearly-Periodic circuit simulation
WP 2: Fast and scalable numerical methods for Transient circuit simulation
WP 3: New numerical techniques to speed up Parametric Analyses and to reduce the number of required Monte Carlo runs