WP 1: Innovative numerical methods for Nearly-Periodic circuit simulation
PhD Candidate
Technical Gap
Analog designers have a wide variety of IP blocks to design and validate (DAC, ADC, PLL, VCO, etc.) targeting various technologies and embedded in many different products. The D&V process of ICs incorporating them heavily relies on Spice simulation pre and post-layout. There is a constant request to increase the simulation speed, while keeping a high accuracy in order to run more tests and perform systematic Monte Carlo or other statistical methods. There are several types of circuits (PLLs/DLLs, DC-DC converters, ADC/DAC, filters, regulators, etc.) for which most of the Spice and FasterSpice engines have very long simulation time that make their systematic use impracticable in the D&V phase. These are still medium size circuits (1,000 - 10,000 active devices, e.g. transistors and 1,000 – 100,000 linear devices) but designers wants to simulate for a period of physical time that is orders of magnitudes higher than the characteristic time of the circuit meaningful phenomena (e.g. at 45nm for instance, the rise/fall time is 10ps while the PLL calibration/lock is 1ms). It is typical to have weeks of simulation even in multi-threaded mode, which inhibits large campaigns of tests and any Monte Carlo analysis. In fact, these kind of circuits are described by stiff equations under the mathematical point of view, i.e. equations characterized by having widely different time constants (fast and slow-varying dynamics). Consequently, the simulation of this kind of circuits is very time consuming because a huge number of time points are calculated. In fact, since some signals vary rapidly and a reliable transient noise analysis is needed, the numerical algorithms involved during the Transient simulation need to drastically reduce the step size of the numerical integration process, in order to produce a Local Truncation Error (LTE), caused by approximating differential equations with difference ones, within a certain threshold. Also, due to eventual strong non-linearities of some components, the systems become even more complex, resulting in a more expensive simulation time in the various analysis processes. We need to take into account these behaviours, in order to accurately evaluate the dynamics of interest (node voltages, branch currents, jitter, etc..).
Target
The main goal is to decrease the Transient simulation time for nearly-periodic circuits from 1 week to 2 hours (70x speed-up).
In particular, we will use:
- Vector extrapolation techniques to adaptively skip the computation of some signal’s time points (without loss of accuracy): since the slow-varying signals at certain nodes of the circuits will have a larger step size with respect to the fast-varying ones, one can think of speeding up the simulation by skipping the computation of the slow-varying variables (node voltages and branch currents) for some discrete time points, required by the fast-varying signals only, and use interpolation methods to reconstruct the solutions of the slow part at those points needed by the fast dynamics.
- Alternatively to the previous single-time dimension method, it will be useful to exploit a multitime approach (from DAE to multi-rate PDAE, as in Adaptive Multi-Rate Wavelet Method for Circuit Simulation) to represent and simulate stiff circuits that exhibit multi-time scales, using envelope circuit equation formulation to have a two-dimensions (split) signal representation;
- Efficient mathematical methods to describes nonlinear devices, such as the Perturbation Projection Vector (PPV) technique for oscillators (e.g., for the Voltage-Controlled Oscillator (VCO) present in a Phase-Locked Loop (PLL) circuit), which helps to further speedup the simulation time.
- Since time performance is a key requisite of the algorithm (stability and accuracy are obvious), it has to be implemented with a multi-threaded programming language (such as Pthread, a set of C language programming types and procedure calls), to exploit the powerful of the multi-core computers parallelism.