WP 3: New numerical techniques to speed up Parametric Analyses and to reduce the number of required Monte Carlo runs

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PhD Candidate

Mr. Anuj Tyagi

Technical Gap

One of the biggest challenges in analog/mixed-signal IC design is uncertainty in electrical behavior and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced nodes (thousands of design and process parameters) that will be needed to meet demands in high-growth areas, like mobile computing. In conventional custom IC design flows, there is little observability into the electrical impact of physical design decisions until the layout is complete. Then, the design intent has to be verified through parasitic extraction and circuit simulation. The combination of electrical uncertainty with increasing sensitivity of AMS designs to parasitic and layout-dependent effects can result in significantly higher turnaround times and more conservative designs that sacrifice performance for reliability. Design productivity and time-to-market are highly dependent on reducing uncertainties introduced during physical design. Uncertainty in the electrical behavior and reliability of AMS chips results from the sensitivity of analog devices to variability and the complex parasitic interactions among devices and interconnect. Additional uncertainty results from manufacturing and layout-dependent geometric dimensions, orientations, and the distances between adjacent devices. In addition, the ability to create identical devices is often critical in meeting electrical performance and design intent from a circuit perspective. Everyone involved in today's SoC design understands that timely physical design of the custom sections primarily RF, analog and mixed-signal, but also certain high-performance digital functions, has become much more difficult as designs move from 65nm to 28nm and further below. Also, uncertainties do not scale in the same way as the scaling of sizes. Part of the challenge is technical: the variability of nanometer silicon is so great that it threatens to make many analog functions non-manufacturable, especially in high-performance designs where parasitic and device characteristics have a critical impact. In fact, scaling towards smaller transistor sizes in order to achieve smaller, faster, lower power and less expensive chips, involves die level reliability issues (e.g. Negative Bias Temperature Instability (NBTI) and Hot Carrier (HC) degradation), as well as increasing process variability (to be dealt with in modern and future CMOS technologies). The lack of adequate knowledge about circuit ageing (i.e., NBTI and HC) can cause unreliable products or unnecessary design margins. Existing solutions (e.g. post-production accelerated stress testing) become too expensive due to an increasing demand for very low failure rates, augmented with evermore reliability and variability problems. A designer needs a statistical circuit analysis tool that includes circuit ageing. Such a tool must be fast (i.e. no more than a few hours of simulation time, even for large circuits) but must also have good simulation accuracy. Moreover, a designer must be able to extract information (i.e. weak-spot detection) to improve his/her design or to implement countermeasures (i.e. circuit tuning). To mitigate the risks associated with moving to advanced nodes (i.e., effects of variability and uncertainty, originating from design, manufacturing, layout, and parasitics), IC design teams will require EDA solutions that reduce electrical uncertainty and ensure design intent is preserved during custom design.


The main goal is to develop new numerical techniques to speed up parametric analyses in the time domain and to reduce the number of required Monte Carlo runs.
To this aim, we will develop methods to:

  • Determine the most "dominant" parameters while combining exact/accurate simulations with approximation outcomes. From the "many" parameters (design, manufacturing process, and operating parameters) we must come down to the "20-50 most dominating" ones.
  • Importance Sampling techniques will be considered to reduce the number of MC runs and to estimate the probability of extremely rare events.
  • A metamodel will be used to accelerate the MC simulations